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AES-NI

Definition

AES New Instructions: hardware AES acceleration introduced on Intel Westmere (2010) and AMD Bulldozer (2011) and now ubiquitous. Single-cycle round operations make AES-128-GCM run at multiple GB/s per CPU core and produce constant-time, side-channel-resistant code.

Full form
AES New Instructions
Intel introduction
Westmere, 2010
AMD introduction
Bulldozer, 2011
Throughput
Multiple GB/s per core for AES-128-GCM

Common questions

Why does hardware AES matter for forensic tooling rather than just performance?+

A software AES implementation using lookup tables can leak timing information tied to the key through cache access patterns, whereas AES-NI performs the rounds in fixed-time silicon, closing that side-channel.

Does the absence of AES-NI make an older device's encryption easier to break?+

No, it only makes software AES slower to compute, not weaker; brute-forcing the key remains computationally infeasible regardless of whether the instructions are hardware-accelerated.

Related terms

AEAD
Authenticated Encryption with Associated Data. Combines confidentiality and integrity in one primitive. AES-GCM and ChaCha20-Poly1305 are the two modern standards. TLS 1.3...
Block Cipher
A symmetric cipher that operates on fixed-size blocks (typically 64 or 128 bits) under a key. AES is a 128-bit-block cipher; DES...
Constant-Time Crypto
An implementation whose execution time, memory access pattern and power profile do not depend on the secret key or plaintext. The defence...
Mode of Operation
The wrapping protocol that defines how a block cipher handles arbitrary-length data, what IV or nonce is used, and whether integrity is...
Stream Cipher
A symmetric cipher that produces a pseudo-random keystream which is XORed bit-by-bit or byte-by-byte with the plaintext. RC4 (legacy), ChaCha20 (current). Stream...

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